1. Field of the Invention
The present invention relates to a display device, and more particularly to a liquid crystal display panel and manufacturing method of the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for improving picture quality.
2. Description of the Related Art
Generally, a liquid crystal display device controls the light transmittance of liquid crystal by use of electric field, thereby displaying a picture. The liquid crystal display device includes a liquid crystal display panel containing liquid crystal cells arranged in a matrix type and a drive circuit for driving the liquid crystal display panel. The liquid crystal display panel includes a thin film transistor array substrate and a color filter array substrate that face each other, a spacer for keeping a fixed cell gap between the two substrates, and a liquid crystal filled into the cell gap.
The thin film transistor array substrate includes gate lines and data lines, a thin film transistor as a switch device at each crossing of the gate lines and the data lines, a pixel electrode in each liquid crystal cell connected to the thin film transistor, and an alignment film. The gate lines and the data lines receive signals from drive circuits through gate pads and data pads, respectively. The thin film transistor supplies a pixel voltage signal, which is supplied to the data line, thereby to the pixel electrode in response to a scan signal supplied to the gate line.
The color filter array substrate includes color filters respectively positioned for each liquid crystal cell, a black matrix for dividing the color filters and reflecting an external light, a common electrode for commonly supplying a reference voltage to the liquid crystal cells, and an alignment film.
The thin film transistor array substrate and the color filter array substrate are made separately and then bonded together. A liquid crystal is injected in the cell gap between the thin film transistor array substrate and the color filter array substrate and then the cell gap is sealed, thereby completing the liquid crystal display panel.
FIG. 1 is a plan view illustrating a thin film transistor array substrate of the related art, and FIG. 2 is a cross-sectional diagram of the thin film transistor array substrate shown in FIG. 1 along line I-I′. The thin film transistor array substrate shown in FIGS. 1 and 2 includes a gate line 2 and a data line 4, which are formed on a lower substrate 42 to cross each other with a gate insulating film 44 therebetween, a thin film transistor 6 (hereinafter, referred to as ‘TFT’) is connected to the gate line 2 and the data line 4, and a pixel electrode 18 is connected the TFT 6 in a pixel cell defined by the gate line 2 and the data line 4. And, the TFT array substrate includes a storage capacitor 20 overlapping a part of the pixel electrode 18 and the pre-stage gate line 2, which is the gate line of an adjacent pixel cell.
The TFT 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, a drain electrode 12 connected to the pixel electrode 18, and an active layer 14 that overlaps the gate electrode 8 and forms a channel between the source electrode 10 and the drain electrode 12. The active layer 14 is overlapped by the data line 4, the source electrode 10 and the drain electrode 12. Ohmic contact layers 48 are formed between the active layer 14 and each of the data line 4 and the source electrode 10 to form ohmic contacts between the active layer 14 and each of the data line 4 and the source electrode 10. The TFT 6 switches a pixel voltage signal from the data line 4 to the pixel electrode 18 in response to a gate signal supplied to the gate line 2.
The pixel electrode 18 is connected to the drain electrode 12 of the TFT 6 through a contact hole 16 which penetrates the passivation film 50. The pixel electrode 18 generates a potential difference with the common electrode formed on the color filter array substrate (not shown) with the pixel voltage. The potential difference causes liquid crystal molecules located between the TFT array substrate and the color filter array substrate to rotate by dielectric anisotropy, and transmits the light from a light source through the pixel electrode and the color filter array substrate.
The storage capacitor 20 is formed by the pixel electrode 18 overlapping the pre-stage gate line 2. A gate insulating film 44 and a passivation film 50 are located between the gate line 2 and the pixel electrode 18. The storage capacitor 20 maintains the pixel voltage on the pixel electrode 18 until the next pixel voltage is applied.
FIGS. 3A to 3D are cross-sectional diagrams illustrating a fabricating method of the thin film transistor array substrate shown in FIG. 2. First, a gate metal layer is patterned by a photolithography process and an etching process after forming the gate metal layer on a lower substrate 42 by a deposition method, such as sputtering, to form a gate pattern having the gate line 2 and the gate electrode 8, as shown in FIG. 3A.
A gate insulating film 44 is formed by a deposition method, such as plasma enhanced chemical vapor deposition (PECVD), on the lower substrate where the gate pattern is formed. An amorphous silicon layer, an n+ amorphous silicon layer and a source/drain metal layer are sequentially formed on the lower substrate 42 where the gate insulating film 44 is formed. A semiconductor pattern 45, including the ohmic contact layer 48 and the active layer 14, and a source/drain pattern 4/10/12, including the data line 4, the source electrode 10, the drain electrode 12, are formed on the semiconductor pattern 45 through a photolithography process using a diffractive mask and an etching process, as shown in FIG. 3B. On the other hand, the semiconductor pattern 45 can be formed separately from the source/drain pattern by use of a separate mask process.
A passivation film 50 is formed over the surface of the lower substrate 42, including the semiconductor pattern 45 and the source/drain pattern 4/10/12, by a deposition method, such as PECVD. The passivation film 50 is then patterned by a photolithography and etching process after forming the passivation film 50, thereby forming a contact hole 16, as shown in FIG. 3C. The contact hole 16 is formed to penetrate the passivation film 50 so as to expose the drain electrode 12.
A transparent electrode material is form over the entire surface of the passivation film 50 by a deposition method, such as sputtering. The transparent electrode material is then patterned by a photolithography and etching process to form the pixel electrode 18, as shown in FIG. 3D. The pixel electrode 18 is electrically connected to the drain electrode 12 through the contact hole 16. Further, the pixel electrode 18 is formed to overlap the pre-stage gate line 2 with the gate insulating film 44 and the passivation film 50 therebetween, thereby forming a storage capacitor 20.
FIG. 4 is a waveform diagram representing a voltage drop in accordance with locations of a common voltage and voltages supplied to the liquid crystal display panel. In the TFT array substrate, as shown in FIG. 4, a gate voltage Vg greater than a threshold voltage is supplied to the gate electrode 8 of the TFT 6 and a data voltage Vd is supplied to the source electrode 10. Further, a DC common voltage Vcom is applied to the common electrode that is located on the color filter array substrate in a TN mode liquid crystal display panel or on the IPS mode TFT array substrate in the liquid crystal display panel. Accordingly, a channel is formed between the source electrode 10 and the drain electrode 12 of the TFT 6 and the data voltage Vd is charged into the storage capacitor 20 through the source electrode 10 and the drain electrode 12 of the TFT.
The size of the common voltage Vcom supplied to the common electrode is decreased in accordance with the increase of line resistance as each pixel cell becomes farther away from the common voltage supplier. Thus, a voltage difference (d) is generated between an effective common voltage value (A) applied to the pixel cell close to the common voltage supplier and an effective common voltage value (B) applied to the pixel cell in a place remote from the common voltage supplier. For example, the common voltage Vcom in the liquid crystal display panel of TN mode is supplied to the common electrode formed across the entire surface of the color filter array substrate from conductors at an the outer part of the liquid crystal display panel such that the effective common voltage value becomes smaller as it goes toward the center of the liquid crystal display panel from the outer part of the liquid crystal display panel. Due to the non-uniformity of the common voltage, a picture difference for each location can be generated in the liquid crystal display panel 160, which can create a residual image and/or flicker.